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? semiconductor components industries, llc, 2007 june, 2007 - rev. 8 1 publication order number: nb100lvep221/d nb100lvep221 2.5v/3.3v?1:20 differential hstl/ecl/pecl clock driver description the nb100lvep221 is a low skew 1-to-20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. the two clock inputs are dif ferential ecl/pecl; clk1/clk1 can also receive hstl signal levels. the lvpecl input signals can be either differential configuration or single-ended (if the v bb output is used). the lvep221 specifically guarantees low output-to-output skew. optimal design, layout, and processing minimize skew within a device and from device to device. to ensure tightest skew, both sides of differential outputs should be terminated identically into 50 even if only one output is being used. if an output pair is unused, both outputs may be left open (unterminated) without affecting skew. the nb100lvep221, as with most other ecl devices, can be operated from a positive v cc supply in lvpecl mode. this allows the lvep221 to be used for high performance clock distribution in +3.3 v or +2.5 v systems. in a pecl envi ronment, series or thevenin line terminations are typically used as they require no additional power supplies. for more information on pecl terminations, designers should refer to application note and8020/d. the v bb pin, an internally generated vo ltage supply, is available to this device only. for single- ended lv pecl input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5ma. when not used, v bb should be left open. single- ended clk input operation is limited to a v cc 3.0 v in lvpecl mode, or v ee -3.0 v in necl mode. features ? 15 ps typical output-to-output skew ? 40 ps typical device-to- device skew ? jitter less than 2 ps rms ? maximum frequency > 1.0 ghz typical ? thermally enhanced 52-lead lqfp and qfn ? v bb output ? 540 ps typical propagation delay ? lvpecl and hstl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = -2.375 v to -3.8 v ? q output will default low with inputs open or at v ee ? pin compatible with motorola mc100ep221 ? pb-free packages are available* *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. lqfp-52 fa suffix case 848h marking diagram* *for additional marking information, refer to application note and8002/d. http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. ordering information a = assembly location wl = wafer lot yy = year ww = work week g = pb-free package nb100 lvep221 awlyywwg 1 qfn-52 mn suffix case 485m 152 nb100 lvep221 awlyywwg 1 52 52
nb100lvep221 http://onsemi.com 2 q9 q9 q8 q7 q7 q6 q15 40 41 42 43 44 45 46 47 25 24 23 22 21 20 19 12345678 39 38 37 36 35 34 33 32 26 q15 q14 q14 q13 q13 q12 q12 q2 q3 q3 q4 q4 q5 q5 v cc0 all v cc , v cco , and v ee pins must be externally connected to appropriate power supply to guarantee proper operation. the thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit, capable of transferring 1.2 watts. this exposed pad is electrically connected to v ee internally. figure 1. 52-lead lqfp pinout (top view) clksel clk0 clk1 clk1 nb100lvep221 clk0 q19 q19 q18 q18 910111213 48 49 50 51 52 31 30 29 28 27 18 17 16 15 14 q17 q17 q16 q16 v cc0 q0 q1 q1 q2 q0 v cc0 v cc v bb v ee q6 q8 q11 q11 q10 q10 v cc0
nb100lvep221 http://onsemi.com 3 figure 2. 52-lead qfn pinout (top view) vcc0 q0 q1 q1 q2 q2 q 3 q4 q4 vcc0 vcc0 q6 q3 q5 q5 vcc clk1 q8 q9 q11 q11 q17 q14 q13 q14 q13 q16 1 2 3 4 5 6 7 8 9 10 11 12 13 clksel clk0 clk0 vbb clk1 vee q19 q19 q18 q18 14 15 16 17 18 19 20 21 22 23 24 25 26 q17 q16 q15 q15 q12 q12 vcc0 39 38 37 36 35 34 33 32 31 30 29 28 27 q10 q10 q9 q8 q7 q7 q6 52 51 50 49 48 47 46 45 44 43 42 41 40 q 0 exposed pad (ep) nb100lvep221 v bb 0 1 clk0 clk0 clk1 clk1 clk_sel active input clk0, clk0 clk1, clk1 clk_sel l h table 1. pin description function ecl/pecl differential inputs ecl/pecl or hstl differential inputs ecl/pecl differential outputs ecl/pecl active clock select input reference voltage output positive supply negative supply pin clk0*, clk0 ** figure 3. logic diagram * pins will default low when left open. ** pins will default high when left open. *** the thermally conductive exposed pad on the bottom of the package is electrically connected to v ee internally. v ee v cc q0 - q19 q0 - q19 20 20 clk1*, clk1 ** v ee*** q0:19, q0:19 clk_sel* v bb v cc /v cco table 2. function table
nb100lvep221 http://onsemi.com 4 table 3. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) pb pkg pb-free pkg lqfp-52 qfn-52 level 2 - level 3 level 2 flammability rating oxygen index: 28 to 34 ul 94 v-0 @ 0.125 in transistor count 533 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v -6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 -6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c ja thermal resistance (junction-to-ambient) (see application information) 0 lfpm 500 lfpm lqfp-52 lqfp-52 35.6 30 c/w c/w jc thermal resistance (junction-to-case) (see application information) 0 lfpm 500 lfpm lqfp-52 lqfp-52 3.2 6.4 c/w c/w ja thermal resistance (junction-to-ambient) (note ) 0 lfpm 500 lfpm qfn-52 qfn-52 25 19.6 c/w c/w jc thermal resistance (junction-to-case) (note ) 2s2p qfn-52 21 c/w t sol wave solder pb pb-free 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nb100lvep221 http://onsemi.com 5 table 5. lvpecl dc characteristics v cc = 2.5 v; v ee = 0 v (note 2) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 100 125 150 104 130 156 116 145 174 ma v oh output high voltage (note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 3) 555 680 900 555 680 900 555 680 900 mv v ih input high voltage (single-ended) (note 4) 1335 1620 1335 1620 1275 1620 mv v il input low voltage (single-ended) (note 4) 555 900 555 900 555 900 mv v ihcmr input high voltage common mode range (differential configuration) (note 5) clk0/clk0 clk1/clk1 1.2 0.3 2.5 1.6 1.2 0.3 2.5 1.6 1.2 0.3 2.5 1.6 v v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary + 0.125 v to -1.3 v. 3. all outputs loaded with 50 to v cc - 2.0 v. 4. do not use v bb at v cc < 3.0 v. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif feren\ tial input signal. table 6. lvpecl dc characteristics v cc = 3.3 v; v ee = 0 v (note 6) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 100 125 150 104 130 156 116 145 174 ma v oh output high voltage (note 7) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 7) 1355 1480 1700 1355 1480 1700 1355 1480 1700 mv v ih input high voltage (single-ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single-ended) 1355 1700 1355 1700 1355 1700 mv v bb output reference voltage (note 8) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 9) clk0/clk0 clk1/clk1 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 1.2 0.3 3.3 1.6 v v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. input and output parameters vary 1:1 with v cc . v ee can vary + 0.925 v to -0.5 v. 7. all outputs loaded with 50 to v cc - 2.0 v. 8. single-ended input operation is limited v cc 3.0 v in lvpecl mode. 9. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
nb100lvep221 http://onsemi.com 6 table 7. lvnecl dc characteristics v cc = 0 v, v ee = -2.375 v to -3.8 v (note 10) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current 100 125 150 104 130 156 116 145 174 ma v oh output high voltage (note 11) -1 145 -1020 -895 -1 145 -1020 -895 -1 145 -1020 -895 mv v ol output low voltage (note 11) -1945 -1820 -1600 -1945 -1820 -1600 -1945 -1820 -1600 mv v ih input high voltage (single-ended) -1 165 -880 -1 165 -880 -1 165 -880 mv v il input low voltage (single-ended) -1945 -1600 -1945 -1600 -1945 -1600 mv v bb output reference voltage (note 12) -1525 -1425 -1325 -1525 -1425 -1325 -1525 -1425 -1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 13) clk0/clk0 clk1/clk1 v ee + 1.2 v ee + 0.3 0.0 -0.9 v ee + 1.2 v ee + 0.3 0.0 -0.9 v ee + 1.2 v ee + 0.3 0.0 -0.9 v v i ih input high current 150 150 150 a i il input low current clk clk 0.5 -150 0.5 -150 0.5 -150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. input and output parameters vary 1:1 with v cc . 11. all outputs loaded with 50 to v cc -2.0 v. 12. single-ended input operation is limited v ee -3.0v in necl mode. 13. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 8. hstl dc characteristics v cc = 3.3 v; v ee = 0 v symbol characteristic 0 c 25 c 85 c unit min typ max min typ max min typ max v ih input high voltage clk1/clk1 v x +100 1600 v x +100 1600 v x +100 1600 mv v il input low voltage clk1/clk1 -300 v x -100 -300 v x -100 -300 v x -100 mv v x differential configuration cross point voltage 680 900 680 900 680 900 mv i ih input high current -150 150 -150 150 -150 150 a i il input low current clk1 clk1 -150 -250 -150 -250 -150 -250 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
nb100lvep221 http://onsemi.com 7 table 9. ac characteristics v cc = 0 v; v ee = -2.375 to -3.8 v or v cc = 2.375 to 3.8 v; v ee = 0 v (note 14) symbol characteristic -40 c 25 c 85 c unit min typ max min typ max min typ max v opp differential output voltage (figure 4) f out < 50 mhz f out < 0.8 ghz f out < 1.0 ghz 550 550 500 700 700 700 600 550 500 700 700 700 600 500 400 700 700 600 mv mv mv t plh /t phl propagation delay (differential configuration) clk0-qx clk1-qx 540 590 600 640 540 590 660 710 540 590 750 800 ps ps t skew within-device skew (note 15) device-to-device skew (note 16) 15 40 50 200 15 40 50 200 15 40 50 200 ps ps t jitter random clock jitter (rms) (figure 4) 1 2 1 2 1 2 ps v pp input swing (differential configuration) (note 17) (figure 5) clk0 clk1 hstl 400 300 800 800 1200 1000 400 300 800 800 1200 1000 400 300 800 800 1200 1000 mv mv dco output duty cycle 49.5 50 50.5 49.5 50 50.5 49.5 50 50.5 % t r /t f output rise/fall time (20%-80%) 100 200 300 100 200 300 150 250 350 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. measured with 750 mv source (lvpecl) or 1 v (hstl) source, 50% duty cycle clock source. all outputs loaded with 50 to v cc -2 v. 15. skew is measured between outputs under identical transitions and conditions on any one device. 16. device-to-device skew for identical transitions, outputs and v cc levels. 17. v pp is the differential configuration input voltage swing required to maintain ac characteristics.
nb100lvep221 http://onsemi.com 8 200 300 400 500 600 700 800 900 figure 4. output voltage (v opp )/jitter versus input frequency (v cc - v ee = 3.3 v @ 25 c) f in , input frequency (ghz) v opp (mv) t jitter ps (rms) 0.1 0.2 0.4 0.6 0.8 1.0 10 9 8 7 6 5 4 3 2 1 0 figure 5. lvpecl differential input levels v ih (diff) v il (diff) v ee v cc (lvpecl) v ih (diff) v il (diff) v ee v cco (hstl) figure 6. hstl differential input levels v ihcmr v pp v pp v x figure 7. typical termination for output driver and device evaluation (see application note and8020/d - termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc - 2.0 v
nb100lvep221 http://onsemi.com 9 applications information using the thermally enhanced package of the nb100lvep221 the nb100l vep221 uses a thermally enhanced 52-lead lqfp package. the package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. this exposed metal pad will provide the low thermal impedance that supports the power consumption of the nb100lvep221 high-speed bipolar integrated circuit and will ease the power management task for the system design. in multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the nb100lvep221. the size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. however, the solderable area should be at least the same size and shape as the exposed pad on the package. direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. the thermal vias will connect the exposed pad of the package to internal copper planes of the board. the number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. the recommended thermal land design for nb100lvep221 applications on multi-layer boards comprises a 4 x 4 thermal via array using a 1.2 mm pitch as shown in figure 8 providing an efficient heat removal path. figure 8. recommended thermal land pattern all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 the via diameter should be approximately 0.3 mm with 1oz. copper via barrel plating. solder wicking inside the via may result in voiding during the solder process and must be avoided. if the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. this will supply enough solder paste to fill those vias and not starve the solder joints. the attachment process for the exposed pad package is equivalent to standard surface mount packages. figure 9, recommended solder mask openings, shows a recommended solder mask opening with respect to a 4 x 4 thermal via array. because a lar ge solder mask opening may result in a poor rework release, the opening should be subdivided as shown in figure 9. for the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered. figure 9. recommended solder mask openings all units mm thermal via array (4 x 4) 1.2 mm pitch 0.3 mm diameter exposed pad land pattern 4.6 4.6 0.2 1.0 1.0 0.2 proper thermal management is critical for reliable system operation. this is especially true for high-fanout and high output drive capability products. for thermal system analysis and junction temperature calculation, the thermal resistance parameters of the package are provided: table 10. thermal resistance * lfpm ja c/w jc c/w 0 35.6 3.2 100 32.8 4.9 500 30.0 6.4 * junction to ambient and junction to board, four-conductor layer test board (2s2p) per jesd 51-8 these recommendations are to be used as a guideline, only. it is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. the exposed pad of the nb100lvep221 package is electrically shorted to the substrate of the integrated circuit and v ee . the thermal land should be electrically connected to v ee .
nb100lvep221 http://onsemi.com 10 ordering information device package shipping ? nb100lvep221fa lqfp-52 160 units / tray NB100LVEP221FAG lqfp-52 (pb-free) 160 units / tray nb100lvep221far2 lqfp-52 1500 / tape & reel nb100lvep221farg lqfp-52 (pb-free) 1500 / tape & reel nb100lvep221mng qfn-52 (pb-free) 260 units / tray nb100lvep221mnr2g qfn-52 (pb-free) 2000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d - ecl clock distribution techniques an1406/d - designing with pecl (ecl at +5.0 v) an1503/d - eclinps i/o spice modeling kit an1504/d - metastability and the eclinps family an1568/d - interfacing between lvds and ecl an1672/d - the ecl translator guide and8001/d - odd number counters design and8002/d - marking and date codes and8020/d - termination of ecl logic devices and8066/d - interfacing with eclinps and8090/d - ac characteristics of ecl devices
nb100lvep221 http://onsemi.com 11 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: mm. 3. datum plane ?e? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting plane. 4. datum ?x?, ?y? and ?z? to be determined at datum plane datum ?e?. 5. dimensions m and l to be determined at seating plane datum ?t?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum pland ?e?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum d dimension by more than 0.08 (0.003). dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). dim a min max min max inches 10.00 bsc 0.394 bsc millimeters b 10.00 bsc 0.394 bsc c 1.30 1.50 0.051 0.059 d 0.22 0.40 0.009 0.016 f 0.45 0.75 0.018 0.030 g 0.65 bsc 0.026 bsc h 1.00 ref 0.039 bsc j 0.09 0.20 0.004 0.008 k 0.05 0.20 0.002 0.008 l 12.00 bsc 0.472 bsc m 12.00 bsc 0.472 bsc n 0.20 ref 0.008 ref p 0 7 0 7 r 0 --- 0 --- s --- 1.70 --- 0.067 v 12 ref 12 ref w 12 ref 12 ref aa 0.20 0.35 0.008 0.014 ab 0.07 0.16 0.003 0.006 ac 0.08 0.20 0.003 0.008 ad 4.58 4.78 0.180 0.188 ae 4.58 4.78 0.180 0.188 -y- 0.05 (0.002) s 1 b b/2 13 14 26 27 39 40 52 -x- l l/2 -z- m m/2 a a/2 aj aj z 0.20 (0.008) t x-y 4 pl z 0.20 (0.008) e x-y -t- seating plane g ag ag d 52 pl z 0.08 (0.003) m t x-y -e- 0.10 (0.004) t 1 13 14 26 27 39 40 52 exposed pad view ag-ag ad ae detail ah detail ah ???? ???? z 0.08 (0.003) m y t-u s c k v r w n f h p ac 0.25 gage plane 48 pl scale 1:1 lqfp 52 lead exposed pad package case 848h-01 issue a
nb100lvep221 http://onsemi.com 12 package dimensions 52 pin qfn 8x8 case 485m-01 issue a c 0.15 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. a d e b c 0.08 a1 a3 a d2 l note 3 c 0.15 2x 2x seating plane c 0.10 a2 c e2 52 x e 1 13 14 26 27 39 40 52 b 52 x a 0.10 b c 0.05 c dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a2 0.60 0.80 a3 0.20 ref b 0.18 0.30 d 8.00 bsc d2 6.50 6.80 e 8.00 bsc e2 6.50 6.80 e 0.50 bsc k 0.20 --- ref k 52 x l 0.30 0.50 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 nb100lvep221/d literature fulfillment : ?literature distribution center for on semiconductor ?p.o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative eclinps is a trademark of semiconductor components industries, llc (scillc).

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